DEVELOPMENT OF MOBILENET V1 USING FPGA

Abstract

Mobile Net V1 is a compact and efficient convolutional neural network (CNN) architecture designed for mobile and embedded systems, where power and processing capabilities are often limited. To address the challenges posed by standard convolutions which are computationally expensive. Mobile net V1 adopts depth wise separable convolutions, a technique that significantly reduces both the model size and Computational load. This method breaks the convolution process into two distinct steps, a depth wise convolution, which applies one filter per input channel and a point wise convolution thatuses 1x1 Kernels to merge the depth wise outputs acrosschannels. This separation minimizes computation while preserving accuracy, makingit suitable for real timetasks suchas object detectionand image classification onedge devices. Inthis project, we present a hardware implementation of the keybuilding blocks of Mobile Net V1 using Verilog HDL.Particularly the design was placed on the optimization of the depth wise and point wise convolution modules at the hardware level. We used the Vivado 2018.2 design suite for simulation and functional verification. The results confirm that our design is capable of performing neural network inference directly on FPGAs, providing a power efficient and practical solution for at the edge. This work underscores the value of hardware acceleration in enabling deep learning on low-resource platform and performed synthesis, implementation further the code was dumped in the hardware, the target device was KC705 Kintex family.