MACHINE LEARNING – BASED AUTOMATED VERIFICATION AND PREDICTIVE BUG DETECTION IN RTL AND PHYSICAL LAYOUT DESIGNS: A LITERATURE SURVEY

Abstract

The growing complexity of modern VLSI systems has significantly increased the burden on conventional verification and validation techniques. Traditional approaches struggle to meet today’s stringent requirements related to time-to-market, cost efficiency, and design reliability. In recent years, Machine Learning (ML) has emerged as a powerful enabling technology capable of transforming verification workflows. By learning from historical design and verification data, ML techniques can automate regression analysis, guide intelligent test generation, and predict defects early at both the Register Transfer Level (RTL) and physical layout stages. This paper presents a comprehensive literature survey of ML-driven automated verification and predictive bug detection methodologies. The reviewed research spans supervised, unsupervised, ensemble, graph-based, and reinforcement learning techniques applied to verification planning, directed stimulus generation, RTL defect prediction, security-aware RTL analysis, routing congestion estimation, design rule checking (DRC) prediction, placement optimization, and early power–performance–area (PPA) estimation. The survey also critically examines modeling strategies, dataset limitations, evaluation metrics, deployment constraints, and integration challenges within industrial Electronic Design Automation (EDA) flows. Finally, research gaps related to dataset scarcity, cross-design generalization, interpretability, and lifecycle integration are identified, highlighting promising directions for future intelligent verification ecosystems.