DYNAMIC SLEEP-CONTROLLED PR9T SRAM CELL FOR LOW LEAKAGE AND POWER-BALANCED MEMORY DESIGN

Abstract

This paper presents the transistor-level implementation, transient functional verification, and supply-current analysis of the PMOS-Reading 9T (PR9T) SRAM cell in 45 nm Cadence Virtuoso technology. The PR9T architecture features a single-ended write path, a power-gated write-support pair, a decoupled PMOS-based read path on the complementary storage node (QB), and a leakage-balancing transistor (MAD) is designed . Transient simulations verify all six SRAM operations: write-1, hold-1, read-1, write-0, hold-0, and read-0. Control-signal waveforms confirm correct synchronization of the write and read paths . These results establish a functional and analytical foundation for leakage-aware SRAM evaluation.