IMPLEMENTATION OF A LIGHTWEIGHT CHACHA20 ENCRYPTION–DECRYPTION CORE ON SPARTAN-7 FPGA

Abstract

Cryptography is crucial to protecting modern communication systems because it ensures data integrity and confidentiality. In this work, a small ChaCha20 encryption–decryption core is implemented using a Xilinx Spartan-7 (XC7S15FTGB196- 1) FPGA-powered PINE-S7 development board. The pipeline stages and quarter-round structure are optimized in the proposed architecture to achieve low power consumption and high through- put. The key expansion, encryption, and decryption modules were developed and tested in the Xilinx Vivado environment using Virtual Input Output (VIO) for real-time validation. Operating at a clock frequency of 100 MHz, the design has a maximum throughput of 4.27 Gbps and a total power consumption of 46 mW. The results demonstrate that power, performance, and resource consumption are all successfully matched, qualifying the recommended design for Internet of Things and low-power embedded systems.